1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a process for depositing materials on a substrate and the structures formed by the materials.
2. Description of the Related Art
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric layers on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where energy-induced chemical reactions take place to produce a desired layer.
CVD processes are useful in forming vertical and horizontal interconnects by a damascene or dual damascene method involving the deposition and patterning of one or more material layers. In the damascene method, one or more dielectric materials, such as the low k dielectric materials (i.e., having a dielectric constant (k) <4.0), are deposited and pattern etched to form the vertical interconnects, also known as vias, and horizontal interconnects, also know as lines. Conductive materials, such as copper containing materials, and other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. Any excess copper containing materials and excess barrier layer material-external to the etched pattern, such as on the field of the substrate, is then removed.
However, when low k material have been used in damascene formation, it has been difficult to produce features with little or no surface defects or feature deformation. It has been observed that low k dielectric materials are often porous and susceptible to being scratched and damaged during removal of conductive materials, which results in defects being formed on the substrate surface. Further, low k materials are often brittle and may deform under conventional polishing processes. One solution to limiting or reducing surface defects and deformation is to deposit a hardmask over the exposed low k materials prior to patterning and etching feature definitions in the low k materials. The hardmask is resistive to damage and deformation. The hardmask may also protect the underlying low k materials during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing techniques or etching techniques, thereby reducing defect formation and feature deformation. The hardmask may then be removed following planarization prior to subsequent processing of the substrate.
Additionally, in the damascene process described above, patterns are formed using conventional lithographic techniques in which a layer of energy sensitive resist is formed over a stack of material layers on a substrate, an image of a pattern is introduced into the energy sensitive resist material, and the pattern introduced into the energy sensitive resist material is transferred into one or more layers of the material stack formed on the substrate using the layer of energy sensitive resist as a mask.
The pattern introduced into the energy sensitive resist can be transferred into one or more layers of the material stack using a chemical etchant. The chemical etchant is designed to have a greater etch selectivity for the material layers of the stack than for the energy sensitive resist. That is, the chemical etchant etches the one or more layers of the material stack at a much faster rate than it etches the energy sensitive resist. The faster etch rate for the one or more material layers of the stack typically prevents the energy sensitive resist material from being consumed prior to completion of the pattern transfer.
As the pattern dimensions are reduced, the thickness of the energy sensitive resist must correspondingly be reduced in order to control pattern resolution. Such thinner resist materials (less than about 6000 Å) can be insufficient to mask underlying material layers during a pattern transfer step using a chemical etchant. A hardmask layer as described above may be used between the energy sensitive resist material and the underlying material layers to facilitate pattern transfer into the underlying material layers. However, in some applications for forming semiconductor structures, it is difficult to remove hardmask materials from the substrate surface and the remaining hardmask material may detrimentally affect semiconductor processing. Further, conventional hardmask materials may not provide sufficient etch selectivity between the material being etched and the hardmask to retain the desired dimensions of the features being formed.
Resist patterning problems are further compounded when lithographic imaging tools having deep ultraviolet (DUV) imaging wavelengths (e. g., less than about 250 nanometers (nm)) are used to generate the resist patterns. The DUV imaging wavelengths improve resist pattern resolution because diffraction effects are reduced at these shorter wavelengths. Additionally, the increased reflective nature of many underlying materials, such as polysilicon, metals, and metal siuicides at such DUV wavelengths, can degrade the resulting resist patterns.
One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist. A number of ARC materials have been suggested for use in combination with energy sensitive resists. However, ARC materials, like hardmask materials are difficult to remove and may leave residues behind that potentially interfere with subsequent integrated circuit fabrication steps.
Therefore, a need exists in the art for a material layer useful for integrated circuit fabrication, which has good etch selectivity and/or anti-reflective properties that may further be removed with little or minimal residues.